首页
未来题库
→
标签
→
REG8
REG8
1.
module SHFT1(CLK,LOAD,DIN,QB); output QB; input CLK,LOAD; input[7:0] DIN; reg[7:0] REG8; always @(posedge CLK)if(LOAD)REG8=DI
2.
module SHFT1(CLK,LOAD,DIN,QB); output QB; input CLK,LOAD; input[7:0] DIN; reg[7:0] REG8; always @(posedge CLK)if(LOAD)REG8=DI